1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a refresh control circuit used for embedded DRAM (Dynamic Random Access Memory) or the like.
2. Description of the Background Art
In DRAM, refresh operations are essential to retain stored data. Japanese Patent Laying-Open No. 3-80493 discloses a memory refresh circuit. This document describes that a refresh end signal of each memory bank serves as a refresh request signal for a bank control circuit at the next stage and the refresh end signal of the memory bank at the last stage is supplied to a refresh request circuit as an acknowledge signal.
In this manner, the refresh operations of the memory banks do not overlap, thereby effectively preventing an error in the system having the memory banks.
Recently, embedded memory has been developed where DRAM and the other large-scale logic circuit or a microprocessor are merged. In this embedded memory, the refresh operation is also required. Unlike a general-purpose DRAM, the embedded memory, however, contains a memory core having a variable memory capacity to support a variety of systems in use.
A region including a memory cell region sandwiched between two sense amplifier bands and a control circuit controlling the memory cell region is called a sub-block. Embedded memory is designed by arranging a necessary number of sub-blocks in accordance with a required memory capacity.
Therefore, the address bit corresponding to a sub-block address is changed each time the number of sub-blocks is changed, and thus the number of bits of a refresh address counter has to be changed. Furthermore, a more complicated change has to be made to the refresh address counter to support the memory capacity where the number of sub-blocks and the total number of word lines is not the power of two.